Senior Mask Design EngineerVerified as a real position

Who we’re looking for

• Diploma in Layout Design or a degree in Electrical/Electronic Engineering
• At least 5 years of hands-on layout design experience
• Experience in layout of high-speed PLLs in advanced Fin-FET process
• Experience using layout design and verification tools
• Experience in floor planning, power grid design, signal routing and repeaters
• Good understanding of clock routing and shielding
• Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
• Ability to learn and ramp on new tools and methodologies
• Ability to estimate realistic schedule, track and report clear progress and status
• Excellent team player and ability to work closely with the circuit design team

What you’ll do

• Layout design of advanced analog and mixed signal macros in deep Sub-Micron Fin-FET technologies.
• Tasks include planning and implementing block and top-level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
• DRC, LVS and other physical verification tools.
• Participate in post-layout circuit performance analysis.
• Estimate and track schedules.

About the position

Join our European Design Center in Prague, Czech Republic and work on cutting-edge CMOS technologies including FinFETs and GAA. We are one of the very few companies in Europe actively designing with these advanced nodes—powering next-generation SoCs for data centers, AI, automotive and low-power IOT and edge AI devices. Based in Prague — one of Europe’s most safe, beautiful and livable cities—you’ll enjoy the unique opportunity to grow your career in a vibrant cultural hub while contributing to world-class semiconductor innovation. Our Prague center plays a pivotal role in developing high-impact mixed-signal IP for global customers.